Z86E30/E31/E40
Z8 4K OTP Microcontroller
Zilog
R248 P01M
R246 P2M
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
P03 - P00 Mode
00 Output
P20 - P27 I/O Definition
01 Input
1X A11 - A8
0
1
Defines Bit as Output
Defines Bit as Input*
* Default After Reset
Stack Selection
0
1
External
Internal
P17 - P10 Mode
00 Byte Output†
01 Byte Input
10 AD7 - AD0
Figure 51. Port 2 Mode Register
F6H:Write Only
11 High-ImpedanceAD7 - AD0,
/AS, /DS, /R//W, A11 - A8,
A15 - A12, If Selected
R247 P3M
External Memory Timing
D7 D6 D5 D4 D3 D2 D1 D0
0
1
Normal
Extended
0
1
Port 2 Open-Drain
Port 2 Push-pullActive
P07 - P04 Mode
00 Output
01 Input
1X A15 - A12
0
1
P31, P32 Digital Mode
P31, P32 Analog Mode
Reset Condition = 0100 1101B
For ROMless Condition = 1011 0110B
† Z86E30/E31 Must be 00
0
1
P32 = Input
P35 = Output
P32 = /DAV0/RDY0
P35 = RDY0//DAV0
Figure 53. Port 0 and 1 Mode Register
F8H:Write Only
00
P33 = Input
P34 = Output
01
10
11
P33 = Input
P34 = /DM
P33 = /DAV1/RDY1
P34 = RDY1//DAV1
†
Z86E30/E31 Only
0
1
P31 = Input (TIN)
R249 IPR
D7 D6 D5 D4 D3 D2 D1 D0
P36 = Output (TOUT)
P31 = /DAV2/RDY2
P36 = RDY2//DAV2
0
P30 = Input
P37 = Output
Interrupt Group Priority
000 Reserved
001 C > A > B
010 A > B > C
011 A > C > B
100 B > C > A
101 C > B > A
110 B > A > C
111 Reserved
Reserved (Must be 0)
Default After Reset = 00H
† Z86E30/E31 Must Be 00
Figure 52. Port 3 Mode Register
F7H:Write Only
IRQ1, IRQ4 Priority (Group C)
0
1
IRQ1 > IRQ4
IRQ4 > IRQ1
IRQ0, IRQ2 Priority (Group B)
0
1
IRQ2 > IRQ0
IRQ0 > IRQ2
IRQ3, IRQ5 Priority (GroupA)
0
1
IRQ5 > IRQ3
IRQ3 > IRQ5
Reserved (Must be 0)
Figure 54. Interrupt Priority Register
F9H:Write Only
DS97Z8X0500
P R E L I M I N A R Y
59
ZILOG [ ZILOG, INC. ]
