Z8018x Family
MPU User Manual
80
Op Code
Fetch Cycle
Last MC
INT0 Acknowledge Cycle
PC is pushed onto stack
Interrupt
Manipulation
Cycle
Vector Lower
Address Read
T1 T2
T1 T2 T3 T1
T3
T1
T2
T2
T3
T3
T1 T2 T3
Ti T1
TW*
T2
TW*
Phi
INT0
Starting address
A0–
A19
M1
SP-1
SP-2
PC
Vector
Vector+1
MREQ
IORQ
RD
WR
Starting Address
(Lower Address)
Starting Address
(Upper Address)
Lower Vector
D0–
D7
ST
PCH
PCL
*Two Wait States are automatically inserted
Figure 40. INT0 Interrupt Mode 2 Timing Diagram
INT1, INT2
The operation of external interrupts INT1 and INT2 is a vector mode
similar to INT0 Mode 2. The difference is that INT1 and INT2 generate
the low-order byte of vector table address using the IL (Interrupt Vector
Low) register rather than fetching it from the data bus. This difference is
UM005001-ZMP0400
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