Z8018x Family
MPU User Manual
78
INT0 Acknowledge Cycle
PC is pushed onto stack
Op Code Fetch Cycle
Last MC
T1 T2 TW* TW* T3 T1 T2 T3 T1 T2 T3 T1 T2 T3
Phi
INT0
A0–
A19
M1
SP-2
0038H
SP-1
PC
MREQ
IORQ
RD
WR
D0–
D7
ST
PCL
PCH
*Two Wait States are automatically inserted
Figure 38. INT0 Mode 1 Timing
INT0 Mode 2
This method determines the restart address by reading the contents of a
table residing in memory. The vector table consists of up to 128 two-byte
restart addresses stored in low byte, high byte order.
UM005001-ZMP0400
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