Z8018x Family
MPU User Manual
76
Last MC
INT0 acknowledge cycle
RST instruction execution
PC is pushed onto stack
*
TW
*
T3
T1
T1 T2
Ti
T2
TW
Ti
T2 T3
T3
T1
Phi
INT0
PC
A0–
A19
M1
SP-1
SP-2
MREQ
RD
WR
IORQ
RST instruction
D0–D7
PCH
PCL
MC: Machine Cycle
*Two Wait States are automatically inserted
The TRAP interrupt occurs if an invalid instruction is fetched
during Mode 0 interrupt acknowledge. (Reference Figure 36.)
Note:
Figure 36. INT0 Mode 0 Timing Diagram
INT0 Mode 1
When INT0 is received, the PC is stacked and instruction execution
restarts at logical address 0038H. Both IEF1 and IEF2 flags are reset to 0,
UM005001-ZMP0400
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