Z8018x Family
MPU User Manual
72
Restart from 0000H
Memory
Read Cycle
3rd Op Code
Fetch Cycle
PC stacking
Op Code
fetch cycle
T1 T2 T3 T1 T2 TTP T3 T1 Ti Ti Ti T1 T2 T3 T1 T2 T3 T1 T2 T3
Phi
A0
–
A19
PC
SP-1
PCH
SP-2
PCL
IX+d, IY+d
0000H
D0
–
D7
Undefined
Op Code
MI
MREQ
RD
WR
Figure 33. TRAP Timing - 3rd Op Code Undefined
External Interrupts
The Z8X180 features four external hardware interrupt inputs:
•
•
•
•
NMI–Non-maskable interrupt
INT0–Maskable Interrupt Level 0
INT1–Maskable Interrupt Level 1
INT2–Maskable Interrupt Level 2
NMI, INT1, and INT2 feature fixed interrupt response modes. INT0 has 3
different software programmable interrupt response modes—Mode 0,
Mode 1 and Mode 2.
NMI - Non-Maskable Interrupt
The NMI interrupt input is edge-sensitive and cannot be masked by
software. When NMI is detected, the Z8X180 operates as follows:
UM005001-ZMP0400
ZILOG [ ZILOG, INC. ]
