Z8018x Family
MPU User Manual
53
CPU Control Register (CCR: 1FH) (Z8S180/L180-Class Processors Only)
Bit
7
6
5
4
3
2
1
0
Bit/Field
Clock STAND BREXT LNPHI STAND LNIO
LNCPU LNAD/
Divide
BY/
IDLE
Enable
BY/
IDLE
Enable
CTL
DATA
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position Bit/Field
R/W Value Description
7
Clock
Divide
R/W
0
1
XTAL/2
XTAL/1
6
STANDBY
/IDLE Mode
R/W
In conjunction with Bit 3
No STANDBY
IDLE after SLEEP
STANDBY after SLEEP
STANDBY after SLEEP 64 Cycle Exit (Quick
Recovery)
00
01
10
11
5
4
3
BREXT
LNPHI
R/W
R/W
R/W
0
1
Ignore BUSREQ in STANDBY/IDLE
STANDBY/IDLE exit on BUSREQ
0
1
Standard Drive
33% Drive on EXTPHI Clock
STANDBY
/IDLE Mode
In conjunction with Bit 6
No STANDBY
IDLE after SLEEP
STANDBY after SLEEP
STANDBY after SLEEP 64 Cycle Exit (Quick
Recovery)
00
01
10
11
UM005001-ZMP0400
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