Z8018x Family
MPU User Manual
50
Table 7. I/O Address Map (Z8S180/Z8L180-Class Processors Only) (Continued)
Address
Register
Mnemonic
Binary
Hex
Page
DMA DMA Source Address Register Ch 0L SAR0L
DMA Source Address Register Ch 0H SAR0H
DMA Source Address Register Ch 0B SAR0B
XX100000
XX100001
XX100010
XX100011
20H
21H
22H
23H
93
93
93
94
DMA Destination Address Register Ch DAR0L
0L
DMA Destination Address Register Ch DAR0H
0H
XX100100
XX100101
24H
25H
94
94
DMA Destination Address Register Ch DAR0B
0B
DMA Byte Count Register Ch 0L
DMA Byte Count Register Ch 0H
BCR0L
BCR0H
XX100110
XX100111
XX101000
XX101001
XX101010
XX101011
XX101100
XX101101
XX101110
XX101111
XX110000
XX110001
XX110010
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
94
94
DMA Memory Address Register Ch 1L MAR1L
DMA Memory Address Register Ch 1H MAR1H
DMA Memory Address Register Ch 1B MAR1B
94
94
94
DMA I/O Address Register Ch 1L
DMA I/O Address Register Ch 1H
DMA I/O Address Register Ch 1
DMA Byte Count Register Ch 1L
DMA Byte Count Register Ch 1H
DMA Status Register
IAR1L
102
102
94
IAR1H
IAR1B
BCR1L
BCR1H
DSTAT
DMODE
DCNTL
94
94
95
DMA Mode Register
97
DMA/WAIT Control Register
101
UM005001-ZMP0400
ZILOG [ ZILOG, INC. ]
