Z8018x Family
MPU User Manual
51
Table 7. I/O Address Map (Z8S180/Z8L180-Class Processors Only) (Continued)
Address
Hex
Register
Mnemonic
IL
Binary
Page
INT
IL Register (Interrupt Vector Low
Register)
XX110011
33H
67
INT/TRAP Control Register
Reserved
ITC
XX110100
XX110101
XX110110
XX110111
XX111000
XX111001
XX111010
XX111011
34H
35H
36H
37H
38H
39H
3AH
3BH
68
88
Refresh Refresh Control Register
Reserved
RCR
MMU MMU Common Base Register
MMU Bank Base Register
MMU Common/Bank Area Register
CBR
61
62
60
BBR
CBAR
I/O
Reserved
XX111101
XX111110
XX111111
3DH
3EH
3FH
Operation Mode Control Register
I/O Control Register
OMCR
ICR
15
42
UM005001-ZMP0400
ZILOG [ ZILOG, INC. ]
