Z8018x Family
MPU User Manual
56
FFFFFH
z
FFFFH
Common Base
Bank Base
Common Area 1
+
+
Bank Area
y
x
Common Area 0
+
0
0000H
x y z
Logical Address Space
00000H
Physical Address Space
Figure 24. Physical Address Transition
MMU Block Diagram
The MMU block diagram is depicted in Figure 25. The MMU translates
internal 16-bit logical addresses to external 20-bit physical addresses.
Internal Address/Data Bus
4
LA12—LA15
MMU Common Base
Register; CBR (8)
MMU Common/Bank Area
Register; CBAR (8)
Memory
Management
Unit
MMU Bank Base
Register; BBR (8)
8
PA12—PA19
LA: Logical Address
PA: Physical Address
Figure 25. MMU Block Diagram
UM005001-ZMP0400
ZILOG [ ZILOG, INC. ]
