Z8018x Family
MPU User Manual
48
Table 7. I/O Address Map (Z8S180/Z8L180-Class Processors Only)
Address
Hex
Register
Mnemonic
Binary
Page
ASCI ASCI Control Register A Ch 0
ASCI Control Register A Ch 1
ASCI Control Register B Ch 0
ASCI Control Register B Ch 1
ASCI Status Register Ch 0
CNTLA0
CNTLA1
CNTLB0
CNTLB1
STAT0
XX000000
XX000001
XX000010
XX000011
XX000100
XX000101
XX000110
XX000111
XX001000
XX001001
XX010010
XX010011
XX011010
XX001011
XX001100
XX001101
XX001010
XX1011
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
12H
13H
1AH
1BH
1CH
1DH
0AH
0BH
125
128
132
132
120
123
118
118
119
119
135
136
137
137
138
138
147
149
ASCI Status Register Ch 1
STAT1
ASCI Transmit Data Register Ch 0
ASCI Transmit Data Register Ch 1
ASCI Receive Data Register Ch 0
ASCI Receive Data Register Ch 1
ASCI0 Extension Control Register 0
ASCI1 Extension Control Register 1
ASCI0 Time Constant Low
TDR0
TDR1
RDR0
RDR1
ASEXT0
ASEXT1
ASTC0L
ASTC0H
ASCT1L
ASCT1H
CNTR
ASCI0 Time Constant High
ASCI1 Time Constant Low
ASCI1 Time Constant High
CSI0
CSI0 Control Register
CSI0 Transmit/Receive Data Register TRD
UM005001-ZMP0400
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