Z8018x Family
MPU User Manual
45
Table 6.
I/O Address Map for Z80180-Class Processors Only (Continued)
Address
Hex
Register
Mnemonic
Binary
Page
Timer Data Register Ch 0 L
Data Register Ch 0 H
Reload Register Ch 0 L
Reload Register Ch 0 H
Timer Control Register
Reserved
TMDR0L
TMDR0H
RLDR0L
RLDR0H
TCR
XX001100
XX001101
XX001110
XX001111
XX010000
XX010001
0CH
0DH
0EH
0FH
10H
11H
159
159
159
159
161
XX010011
XX010100
XX010101
XX010110
XX010111
XX011000
XX011001
13H
14H
15H
16H
17H
18H
19H
Data Register Ch 1 L
Data Register Ch 1 H
Reload Register Ch 1 L
Reload Register Ch 1 H
TMDR1L
TMDR1H
RLDR1L
RLDR1H
FRC
160
160
159
159
172
Others Free Running Counter
Reserved
XX011111
1FH
UM005001-ZMP0400
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