Z8018x Family
MPU User Manual
30
inserted depending on the programmed value in IWI1 and IWI0. Refer to
Table 4.
Table 4.
Wait State Insertion
The Number of Wait States
For INT1,
For NMI
interrupt
acknow ledge
cycles
INT2 and
internal
For INT0
For internal interrupt
interrupts
For external
I/0
acknow ledge acknow ledge w hen M1 is
I/O registers registers
cycles w hen cycles
Low
IWI1 IWI0 accesses
accesses
M1 is Low
(Note 2)
(Note 2)
0
0
0
1
0
1
1
2
3
4
0
2
4
5
6
2
0
(Note 1)
1
1
Note:
1. For Z8X180 internal I/O register access (I/O addresses 0000H-003FH), IWI1 and IWI0 do not
determine wait state (TW) timing. For ASCI, CSI/O and PRT Data Register accesses, 0 to 4 Wait States
(TW) are generated. The number of Wait States inserted during access to these registers is a function of
internal synchronization requirements and CPU state. All other on-chip I/O register accesses (that is,
MMU, DMAC, ASCI Control Registers, for instance.) have no Wait States inserted and thus require only
three clock cycles.
2. For interrupt acknowledge cycles in which M1 is High, such as interrupt vector table read and PC
stacking cycle, memory access timing applies.
WAIT Input and RESET
During RESET, MWI1, MWI0 IWI1 and IWI0, are all 1, selecting the
maximum number of Wait States (TW) (three for memory accesses, four
for external I/O accesses).
UM005001-ZMP0400
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