Z8018x Family
MPU User Manual
34
•
Data Bus, 3-state
SLEEP mode is exited in one of two ways as described below.
•
RESET Exit from SLEEP mode. If the RESET input is held Low for
at least six clock cycles, it exits SLEEP mode and begins the normal
RESET sequence with execution starting at address (logical and
physical) 00000H.
•
Interrupt Exit from SLEEP mode. The SLEEP mode is exited by
detection of an external (NMI, INT0, INT2) or internal (ASCI,
CSI/O, PRT) interrupt.
In case of NMI, SLEEP mode is exited and the CPU begins the normal
NMI interrupt response sequence.
In the case of all other interrupts, the interrupt response depends on the
state of the global interrupt enable flag IEF1 and the individual interrupt
source enable bit.
If the individual interrupt condition is disabled by the corresponding
enable bit, occurrence of that interrupt is ignored and the CPU remains in
the SLEEP mode.
Assuming the individual interrupt condition is enabled, the response to
that interrupt depends on the global interrupt enable flag (IEF1). If
interrupts are globally enabled (IEF1 is 1) and an individually enabled
interrupt occurs, SLEEP mode is exited and the appropriate normal
interrupt response sequence is executed.
If interrupts are globally disabled (IEF1 is 0) and an individually enabled
interrupt occurs, SLEEP mode is exited and instruction execution begins
with the instruction following the SLP instruction. This feature provides a
technique for synchronization with high speed external events without
incurring the latency imposed by an interrupt response sequence.
Figure 21 depicts SLEEP timing.
UM005001-ZMP0400
ZILOG [ ZILOG, INC. ]
