Z8018x Family
MPU User Manual
143
Table 19. ASCI Baud Rate Selection (Continued)
Sampling
Rate
Baud Rate (Example)
(BPS)
General
SS2 SS1 SS0 Divide Divide f = 6.144 f = 4.608 f = 3.072
Prescaler
Divide
Baud Rate
CKA
Clock
PS Ratio DR Rate
Ratio
Ratio MHz
MHz
MHz
I/O Frequency
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
¸ 1
f ¸ 480
960
9600
f ¸ 30
60
2
4
4800
2400
1200
600
300
150
—
1920
120
8
3840
0
I
240
480
960
1920
fc
0
16
16
32
64
—
7680
15360
30720
fc ¸ 16
1
f ¸ 30
—
—
¸ 1 f ¸ 1920
2400
1200
600
300
150
75
f ¸ 30
60
2
4
3840
7680
120
240
480
960
1920
fc
8
15360
30720
61440
122880
fc ¸ 64
0
I
1
64
16
32
64
—
37.5
—
—
—
Baud Rate Generator
(Z8S180/Z8L180-Class Processors Only)
The Z8S180/Z8L180 Baud Rate Generator (BRG) features two modes.
The first is the same as in the Z80180. The second is a 16-bit down
counter that divides the processor clock by the value in a 16-bit time
constant register, and is identical to the DMSCC BRG. This feature
UM005001-ZMP0400
ZILOG [ ZILOG, INC. ]
