Z8018x Family
MPU User Manual
104
Bits 5–3
Reserved. Must be 0.
Bits 2–0
With DIM1, bit 1 of DCNTL, these bits control which request is
presented to DMA channel 1, as described below:
DIM1 IAR18–16 Request Routed to DMA Channel 1
0
0
0
0
0
0
0
000
001
010
011
10X
1X0
111
DREQ1
ASCI0 Tx
ASCI1 Tx
ext CKA0/DREQ0
Reserved
Reserved
Reserved
1
1
1
1
1
1
1
000
001
010
011
10X
1X0
111
ext DREQ1
ASCI0 Rx
ASCI1 Rx
ext CKA0/DREQ0
Reserved
Reserved
Reserved
DMA Operation
This section discusses the three DMA operation modes for channel 0:
•
•
•
Memory to/from memory
Memory to/from I/O
Memory to/from memory mapped I/O
UM005001-ZMP0400
ZILOG [ ZILOG, INC. ]
