ZL50022
Data Sheet
and output encoding laws are set to the same standard, no translation occurs. As the V/D (bit 4) of the Connection
Memory High (CM_H) must be set on a per-channel basis, it is not possible to translate between voice and data
encoding laws.
20.0 Quadrant Frame Programming
By programming the Stream Input Quadrant Frame Registers (SIQFR0 - 31), users can divide one frame of input
data into four quadrant frames and can force the LSB or MSB of every input channel in these quadrants to one or
zero for robbed-bit signaling. The four quadrant frames are defined as follows:
Data Rate
Quadrant 0
Quadrant 1
Quadrant 2
Quadrant 3
2.048 Mbps
4.096 Mbps
8.192 Mbps
16.384 Mbps
Channel 0 - 7
Channel 0 - 15
Channel 0 - 31
Channel 0 - 63
Channel 8 - 15
Channel 16 - 31
Channel 32 - 63
Channel 16 - 23
Channel 32 - 47
Channel 64 - 95
Channel 24 - 31
Channel 48 - 63
Channel 96 - 127
Channel 64 - 127 Channel 128 - 191 Channel 192 - 255
Table 14 - Definition of the Four Quadrant Frames
When the quadrant frame control bits, STIN[n]Q3C2 - 0 (bit 11 - 9), STIN[n]Q2C2 - 0 (bit 8 - 6), STIN[n]Q1C2 - 0 (bit
5 - 3) or STIN[n]Q1C2 - 0 (bit 2 - 0), are set, the LSB or MSB of every input channel in the quadrant is forced to “1”
or “0” as shown by the following table:
STIN[n]Q[y]C[2:0]
Action
0xx
Normal Operation
100
101
110
111
Replaces LSB of every channel in Quadrant y with ‘0’
Replaces LSB of every channel in Quadrant y with ‘1’
Replaces MSB of every channel in Quadrant y with ‘0’
Replaces MSB of every channel in Quadrant y with ‘1’
Note: y = 0, 1, 2, 3
Table 15 - Quadrant Frame Bit Replacement
Note that Quadrant Frame Programming and BER reception cannot be used simultaneously on the same input
stream.
21.0 JTAG Port
The JTAG test port is implemented to meet the mandatory requirements of the IEEE-1149.1 (JTAG) standard. The
operation of the boundary-scan circuitry is controlled by an external Test Access Port (TAP) Controller.
21.1 Test Access Port (TAP)
The Test Access Port (TAP) accesses the ZL50022 test functions. It consists of three input pins and one output pin
as follows:
•
Test Clock Input (TCK) - TCK provides the clock for the test logic. TCK does not interfere with any on-chip
clock and thus remains independent in the functional mode. TCK permits shifting of test data into or out of
the Boundary-Scan register cells concurrently with the operation of the device and without interfering with
the on-chip logic.
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Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
