ZL50022
Data Sheet
15.6 Multiple Period Reference Monitoring
To monitor reference failure based on frequency offset, multi-period checking is performed. Reference validation
time is prescribed by Telcordia GR-1244-CORE and is between 10 and 30 seconds. To meet the criteria for
reference validation time, the time base for multi period monitoring has to be big enough. To implement hysteresis,
the upper limits are split into near upper and far upper limits and the lower limits are split into near lower and far
lower limits. The reference failure is detectable only when the reference passes far limits, but passing is not
detected until the reference is within near limits. The zone between near and far limits, called the “grey zone”, is
required by standards and prevents unnecessary reference switching when the selected reference is close to the
boundary of failure.
The monitor makes a decision about reference validity after two consecutive measurements with respect to its time
base. The time base for multi-period monitoring is 10 seconds. The time base is defined in the number of reference
clock cycles.
The device has two sets of limits, the Stratum 4E default limits and the Relaxed Stratum 4E limits (see Table 12,
“Multi-period Hysteresis Limits” on page 46). The ST4_LIM bit in Table 28, DPLL Control Register (DPLLCR) Bits is
used to select between the two sets of limits.
Stratum 4E Default Limits
(in 10 ns units)
Relaxed Stratum 4E Limits
(in 10 ns units)
Far Upper Limit
Near Upper Limit
Nominal Value
-82.487 ppm
-64.713 ppm
-250 ppm
-240 ppm
0 ppm
Near Lower Limit
Far Lower Limit
64.713 ppm
82.487 ppm
240 ppm
250 ppm
Table 12 - Multi-period Hysteresis Limits
16.0 Microprocessor Port
The device provides access to the internal registers, connection memories and data memories via the
microprocessor port. The microprocessor port is capable of supporting both Motorola and Intel non-multiplexed
microprocessors. The microprocessor port consists of a 16-bit parallel data bus (D15 - 0), 14 bit address bus (A13 -
0) and six control signals (MOT_INTEL, CS, DS_RD, R/W_WR, IRQ and DTA_RDY).
The data memory can only be read from the microprocessor port. For a data memory read operation, D7 - 0 will be
used and D15 - 8 will output zeros.
For a CM_L read or write operation, all bits (D15 - 0) of the data bus will be used. For a CM_H write operation, D4 -
0 of the data bus must be configured and D15 - 5 are ignored. D15 - 5 must be driven either high or low. For a
CM_H read operation, D4 - 0 will be used and D15 - 5 will output zeros.
Refer to Figure 26 on page 94, Figure 27 on page 95, Figure 28 on page 96 and Figure 29 on page 97 for the
microprocessor timing.
17.0 Device Reset and Initialization
The RESET pin is used to reset the ZL50022. When this pin is low, the following functions are performed:
•
•
•
synchronously puts the microprocessor port in a reset state
tristates the STio0 - 31 outputs
drives the STOHZ0 - 15 outputs to high
46
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