ZL50022
Data Sheet
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preloads all internal registers with their default values (refer to the individual registers for default values)
clears all internal counters
17.1 Power-up Sequence
The recommended power-up sequence is for the VDD_IO supply (normally +3.3 V) to be established before the
power-up of the VDD_CORE supply (normally +1.8 V). The VDD_CORE supply may be powered up at the same time
as VDD_IO, but should not “lead” the VDD_IO supply by more than 0.3 V.
17.2 Device Initialization on Reset
Upon power up, the ZL50022 should be initialized as follows:
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Set the ODE pin to low to disable the STio0 - 31 outputs and to drive STOHZ0 - 15 to high
Set the TRST pin to low to disable the JTAG TAP controller
Reset the device by pulsing the RESET pin to zero for longer than 1 µs
After releasing the RESET pin from low to high, wait for a certain period of time (see Note below) for the
device to stabilize from the power down state before the first microprocessor port access can occur
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Program CKIN1 - 0 (bit 6 -5) in the Control Register (CR) to define the frequency of the CKi and FPi inputs
Wait at least 500 µs prior to the next microport access (see Note below)
Use the block programming mode to initialize the connection memory
Release the ODE pin from low to high after the connection memory is programmed
Note: If an external oscillator is used, the waiting time is 500 µs. Without the external oscillator, if CKi is
16.384 MHz, the waiting time is 500 µs; if CKi is 8.192 MHz, the waiting time is 1 ms; if CKi is 4.096 MHz, the
waiting time is 2 ms.
17.3 Software Reset
In addition to the hardware reset from the RESET pin, the device can also be reset by using software reset. There
are two software reset bits in the Software Reset Register (SRR). SRSTDPLL (bit 0) is used to reset the DPLL while
SRSTSW (bit 1) resets the rest of the switch.
18.0 Pseudo-random Bit Generation and Error Detection
The ZL50022 has one Bit Error Rate (BER) transmitter and one BER receiver for each pair of input and output
streams, resulting in 32 transmitters connected to the output streams and 32 receivers associated with the input
streams. Each transmitter can generate a BER sequence with a pattern of 215-1 pseudo-random code (ITU O.151).
Each transmitter can start at any location on the stream and will last for a minimum of 1 channel to a maximum of 1
frame time (125 µs). The BER receivers and transmitters are enabled by programming the RBEREN (bit 5) and
TBEREN (bit 4) in the IMS register. In order to save power, the 32 transmitters and/or receivers can be disabled.
(This is the default state.)
Multiple connection memory locations can be programmed for BER tests such that the BER patterns can be
transmitted for multiple consecutive output channels. If consecutive input channels are not selected, the BER
receiver will not compare the bit patterns correctly. The number of output channels which the BER pattern occupies
has to be the same as the number of channels defined in the BER Length Register (BRLR) which defines how
many BER channels are to be monitored by the BER receiver.
For each input stream, there is a set of registers for the BER test. The registers are as follows:
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BER Receiver Control Register (BRCR) - ST[n]CBER (bit 1) is used to clear the Bit Receiver Error Register
(BRER). ST[n]SBER (bit 0) is used to enable the per-stream BER receiver.
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