ZL50022
Data Sheet
(LDTR) should be programmed with respect to the maximum expected jitter frequency and amplitude on the
selected input references.
The lock status can be monitored through the Reference Change Status Register (RCSR). See Table 37 on
page 70 for the bit description of the Reference Change Status Register (RCSR).
15.2 Maximum Time Interval Error (MTIE)
Several standards require that the output clock of the DPLL may not move in phase more than a certain amount. In
order to meet those standards, a special circuit maintains the phase of the DPLL output clock during reference and
mode rearrangements. The total output phase change or Maximum Timing Interval Error (MTIE) during
rearrangements is less than 31 ns per rearrangement, exceeding Stratum 4E requirements. After a large number of
reference switches, the accumulated phase error can become significant, so it is recommended to use MTIE reset
in such situations, to realign outputs to the nearest edge of the selected reference. The MTIE reset can be
programmed by setting MTR (bit 7) in the Reference Change Control Register (RCCR), as described in Table 36 on
page 69.
15.3 Phase Alignment Speed (Phase Slope)
Besides total phase change, standards also require a certain rate of the phase change of the output clock. The
phase alignment speed is programmable by the user through a value in the Slew Rate Limit Register (SRLR) as
described in Table 35 on page 68. Stratum 4E requires that the phase alignment speed not exceed 81 ns per
1.326 ms (61ppm). The width of the register and the limiter circuitry provide a maximum phase change alignment
speed of 186 ppm. The phase alignment speed default value is 56 ppm.
15.4 Reference Monitoring
The quality of the four input reference clocks is continuously monitored by the reference monitors. There are
separate reference monitor circuits for the four DPLL references. References are checked for short phase (single
period) deviations as well as for frequency (multi-period) deviations with hysteresis.
The Reference Status Register (RSR) reports the status of the reference monitors. The register bits are described
in Table 41 on page 74. The Reference Mask Register (RMR) allows users to ignore the monitoring features of the
reference monitors. See Table 42 on page 75 for details.
15.5 Single Period Reference Monitoring
Values for short phase deviations (upper and lower limit) are programmable through registers. The unit of the binary
values of these numbers is 100 MHz clock period (10 ns). Single period deviation limits are more relaxed than multi
period limits, and are used for early detection of the reference loss, or huge phase jumps.
The values for the upper and lower limits are shown in the following table:
Reference
Frequency
Comment
8 kHz
10UIp-p
0.3UIp-p
0.2UIp-p
0.2UIp-p
0.2UIp-p
0.2UIp-p
0.2UIp-p
1.544 MHz
2.048 MHz
4.096 MHz
8.192 MHz
16.384 MHz
19.44 MHz
Table 11 - Values for Single Period Limits
45
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
