SP5848 Preliminary Information
Absolute maximum Ratings
All voltages referred to Vee at 0V
Characteristic
Value
Conditions
Min
-0.3
Max
7
Units
V
Supply voltages
RF1 input voltage
RF2 input voltage
All I/O ports DC offset
Storage temperature
Junction temperature
Package thermal resistance
chip to ambient
chip to case
Power consumption with all
Vcc =5.5V
2.5
2.5
Vcc+0.3
+125
150
Vp-p
Vp-p
V
°C
°C
Differential
Differential
-0.3
-55
100
30
121
°C/W
°C/W
mW
All ports off
ESD protection
2
kV
Mil std 883 latest revision methood 3015
class 1
Functional Description
Programming Mode
The SP5848 contains two PLL frequency synthesiser
loops, eachindependentlyprogrammablefroma3-wire
bus. The device is optimised for application in double
conversion tuners where synthesiser 1 would form part
of the upconverter and synthesiser 2 part of the down
converter. Both loops are optimised for application in
low phase noise loops and furtherly synthesiser 2 offers
low comparison frequencies. A block diagram is
contained in Figure 1.
The SP5848 is designed to be programmed from a
standard3-wirebusconsistingofclock,dataandenable,
where the serial clock and data lines can be shared with
other devices and the enable line is a unique line for
individual device selection. To simplify programming
each synthesiser is independently addressed, with the
required loop being selected by the LSB bit , which
functions as the address, therefore to fully program the
device two complete data transmissions must be sent.
The device is programmed via a 3-wire bus where data
is fed on serial data and clock lines and is gated by an
enable line. Figure 3 indicates the format of the data.
The sequence and timing of data load is described
below in ‘programming mode’ description. Each
synthesiserisindependentlyaddressableandisdefined
by the LSB bit within the data transmission.
The data format for each transmission is contained in
Figure 3.
Test modes as described in Figure 7, can be invoked by
setting bit T0 in synthesiser 2 data word to a ‘1’ and
sending control data for bits T1-T2. In normal operation
where T0 is set to a ‘0’ bits T1 and T2 do not need to be
transmitted
A common reference frequency source and reference
divider is used to derive the comparison frequency for
both PLL loops. The reference division ratio is
programmable via the data bus as defined in Tables1
and 2.
The charge pump current for each loop is also
programmable via the data bus as defined in Tables 3
and 4
Two switching ports are provided to control switching
functions within the tuner. These ports also access test
signals within the PLL as defined in Figure 7. Ports
power up in high impedance state.
4
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
