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SP5848 参数 Datasheet PDF下载

SP5848图片预览
型号: SP5848
PDF下载: 下载PDF文件 查看货源
内容描述: 2.2 / 1.3GHz的3 - Wire总线的双低相位噪声PLL [2.2/1.3GHz 3-Wire Bus Dual Low Phase Noise PLL]
分类和应用:
文件页数/大小: 10 页 / 500 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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SP5848  
2.2/1.3GHz 3-Wire Bus Dual Low Phase Noise PLL  
Preliminary Information  
DS5076  
ISSUE 1.6  
October 1999  
Features  
Ordering Information  
SP5848/KG/QP1S  
Dual independent PLL frequency synthesisers in a  
single package, optimised for double conversion  
cable tuners, offering improved application  
SP5848/KG/QP1T  
2.2GHz up-synthesiser optimised for low phase  
noise up to comparison frequencies of 4MHz  
1.3GHz down-synthesiser optimised for low phase  
noise AND small step size  
Common reference oscillator and divider with  
independently selectable ratios for each  
synthesiser  
10:1 programmable charge pump current ratio in  
up synthesiser  
3-Wire bus programmable, each synthesiser  
Description  
The SP5848 is a dual PLL frequency synthesizer  
controlled by a 3-wire bus optimised for application in  
double conversion tuners.  
Each synthesiser loop within the SP5848 is  
independently addressable and contains an RF  
programmable divider, phase/frequency detector and  
charge pump/loop amplifier section; a common  
reference frequency oscillator and divider chain is  
provided, whose ratios for each loop are independently  
programmable.  
indepently addressable  
Low power consumption, typ 100mW at 5V  
ESD protection, (Normal ESD handling  
procedures should be observed)  
Both synthesisers are optimised for low phase noise  
performance and in addition synthesiser 2 is capable of  
operation with a low comparison frequency.  
Applications  
TV, VCR, and cable tuning systems  
PUMP 1  
DRIVE 1  
11 BIT  
COUNT  
RF1 INPUT  
16/17  
4 BIT  
COUNT  
PORT P0  
15 BIT LATCH  
2 BIT  
LATCH  
2 BIT  
LATCH  
PORT P1  
DATA  
DATA  
INTERFACE  
CLOCK  
5 BIT  
LATCH  
29  
DIVIDE  
ENABLE  
1 BIT  
LATCH  
16 BIT LATCH  
PUMP 2  
DRIVE 2  
12 BIT  
COUNT  
16/17  
4 BIT  
RF 2 INPUT  
COUNT  
Figure 1 - Block Diagram