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SP5848 参数 Datasheet PDF下载

SP5848图片预览
型号: SP5848
PDF下载: 下载PDF文件 查看货源
内容描述: 2.2 / 1.3GHz的3 - Wire总线的双低相位噪声PLL [2.2/1.3GHz 3-Wire Bus Dual Low Phase Noise PLL]
分类和应用:
文件页数/大小: 10 页 / 500 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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Preliminary Information SP5848  
Electrical Characteristics (continued)  
o
o
T
= -40 C to +80 C, Vcc = 4.5 to 5.5 V, These characteristics are guaranteed by either production test or  
amb  
design. They apply within the specified ambient temperature and supply voltage unless otherwise stated.  
Characteristic  
Pin  
Value  
Typ  
Units  
Conditions  
Min  
30  
Max  
300  
Synthesiser 2 (DOWN)  
RF2 input voltage  
RF2 input impedance  
RF2 division ratio  
Reference division 2  
ratio  
5,6  
5,6  
mVrms 80 -1300MHz  
See Figure 5  
240  
65535  
See Table 2  
Comparison frequency 2  
16.25  
4000  
KHz  
Phase noise degrades above  
250KHz  
Equivalent phase noise  
at phase detector 2  
-144  
dBc/Hz SSB, within loop bandwidth, all  
comparison frequencie up to  
250KHz  
Charge pump 2 output  
current  
Charge pump 2 output  
leakage  
Charge pump 2 drive  
output curent  
2
2
3
See Table 4  
Vpin 2=2V  
Vpin2 = 2V  
3
10  
nA  
0.5  
mA  
Vpin 3 = 0.7V  
Data, clock and enable 12,11,13  
Input high voltage  
Input low voltage  
Input current  
3
0
-10  
Vcc  
0.7  
10  
V
V
µA  
All input conditions  
hysterysis  
0.8  
Vpp  
Clock rate  
11  
500  
KHz  
Bus timing -  
Data set up  
Data hold  
Enable setup  
Enable hold  
Clock to enable  
Reference Oscillator  
Crystal frequency  
External reference input  
frequency  
300  
600  
300  
600  
300  
ns  
ns  
ns  
ns  
ns  
8, 9  
8
2
2
16  
20  
MHz  
MHz  
See Figure 6 for application  
Sinewave coupled through  
10nF blocking capacitor  
Sinewave coupled through  
10nF blocking capacitor  
See note 1  
External reference drive  
8
0.2  
2
0.5  
Vpp  
Outputs ports P0 - P1  
sink current  
1, 20  
mA  
Vport = 0.7V  
leakage current  
10  
µA  
Vport = Vcc  
Note 1 Output ports high impedance on power up, with data, clock and enable at logic 0  
3