P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
1.4 Connection Diagram – 256-BGA Package (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
P_
20
P_
L_A
[13]
L_A
[12]
L_A
[10]
L_A[5] / L_A[2] /
P_C[3] P_C[0]
C_ C_ EC# C_D
MF#
C_D
[3]
C_D
[6]
C_D
[10]
C_D
[13]
P_A
[11]
P_A
[8]
P_A
[6]
P_A
A
B
C
D
E
F
[2]
[3] BS16# RDY#
L_A
[14]
L_A
[11]
L_A
[8]
L_A L_A[3] / C_ CE#
[6] P_C[1]
C_
CM#
C_D
[1]
C_D
[4]
C_D
[7]
C_D
[11]
C_D
[14]
P_A
[10]
P_A
[7]
P_A
[4]
P_
ADS#
P_A
[2]
P_
INT
L_A
[18]
L_A
[16]
L_A
[15]
L_A
[9]
L_A L_A[4] / L_WE C_
[7] P_C[2] [3] WE#
C_
FF#
C_D
[0]
C_D
[5]
C_D
[9]
C_D
[12]
C_D
[15]
P_A
[9]
P_A
[5]
P_A P_ CS# P_ P_RST
[1]
RWC OUT
L_OE L_OE L_A
[1]# [3]#
VDD
C_D
[8]
VDD
(Core)
P_RST
IN#
P_
CLK
VSS VDD VSS VDD VSS VSS
VDD VSS VDD
VSS VDD
VSS
[17] (Core)
L_BWE L_BWE L_WE
[2]# [3]# [1]#
P_D
[31]
P_D
[30]
VSS
VDD
VSS
L_ L_BWE L_BWE
ADSC# [0]#
P_D
[29]
P_D
[28]
P_D
[27]
VDD
[1]#
L_D L_OE
[0]
VDD P_D
(Core) [26]
P_D
[25]
P_D
[24]
G
H
J
[0]#
L_D
[3]
L_D
[2]
L_D L_WE
[1]
P_D
[23]
P_D
[22]
P_D
[21]
VSS
[0]#
L_D
[7]
L_D
[6]
L_D
[4]
L_D
[5]
P_D
[20]
P_D
[19]
P_D
[18]
VDD
L_D
[9]
L_D
[8]
P_D
[17]
P_D
[16]
P_D
[15]
VDD
VSS
K
L
L_D
[10]
L_D
[11]
L_D
[12]
P_D
[12]
P_D
[13]
P_D
[14]
VSS
VDD
L_D
[13]
L_D
[14]
L_D
[15] (Core)
P_D
[9]
P_D
[10]
P_D
[11]
VSS
M
N
P
R
T
L_D
[16]
L_D
[17]
L_D
[18]
P_D
[3]
P_D
[6]
P_D
[7]
P_D
[8]
VSS
L_D
[19]
L_D
[20]
L_D
[21]
VDD P_D
P_D
[4]
P_D
[5]
VDD
(Core)
[2]
L_D
[22]
L_D
[23]
L_D
[24]
L_D
[26]
P_D
[0]
P_D
[1]
VDD
L_D
[25]
L_D
[27]
L_D
[28]
S_REQ S_REQ S_GNT
VSS
VSS
[7]#
[8]#
[8]#
L_D
[29]
L_D
[30]
L_D
[31]
S_D
[4]
VDD
(Core)
S_D
[25]
S_D S_REQ S_GNT S_GNT S_GNT S_GNT
VDD VSS
VSS VDD
VSS VDD VSS
U
V
W
Y
[29]
[1]#
[4]#
[5]#
[6]#
[7]#
L_WE
[2]#
L_
S_
S_D
[0]
S_D
[3]
S_D
[7]
S_D
[10]
S_D
[13]
S_D
[20]
S_D
[23]
S_D
[26]
S_D
[30]
S_REQ S_REQ
VDD
VDD
VDD
CLK TABT#
[4]#
[5]#
L_OE S_MSG S_
[2]#
S_
S_D
[1]
S_D
[5]
S_D
[8]
S_D
[11]
S_D
[14]
S_D
[17]
S_D
[19]
S_D
[22]
S_D
[27]
S_HP S_GNT S_REQ S_GNT
REQ# [1]# [6]# [3]#
VSS
EN# EOF# OVLD#
T_
MODE
S_ S_
IRDY CLK
S_D
[2]
S_D
[6]
S_D
[9]
S_D
[12]
S_D
[15]
S_D
[16]
S_D
[18]
S_D
[21]
S_D
[24]
S_D
[28]
S_D S_REQ S_GNT S_REQ
[31] [2]# [2]# [3]#
© 1998 Vertex Networks, Inc.
8
Rev. 4.5 – February
1999
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
