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SC220C6P 参数 Datasheet PDF下载

SC220C6P图片预览
型号: SC220C6P
PDF下载: 下载PDF文件 查看货源
内容描述: XpressFlow 2020年以太网路由交换机芯片组 [XpressFlow 2020 Ethernet Routing Switch Chipset]
分类和应用: 以太网
文件页数/大小: 34 页 / 616 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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XpressFlow-2020 Series –  
Ethernet Switch Chipset  
SC220  
XpressFlow Engine  
Pin No(s).  
Symbol  
Type  
Name & Functions  
XpressFlow Bus Interface  
185,184,183,182,180,  
179,177,176,175,174,  
172,171,169,168,167,  
P_D[31:0]  
TTL I/O-TS Management Bus – Data Bit [31:0]  
(5VT)  
166,164,163,160,159,  
157,156,154,153,151,  
150,149,148,146,145,  
143,142  
211,210,208,207,205,  
204,203,202,201,199,  
198  
P_A[11:1]  
TTL Input  
(5VT)  
Management Bus – Address Bit [11:1]  
196  
P_ADS#  
P_RWC  
P_RDY#  
P_BS16#  
P_CS#  
TTL Input  
(5VT)  
Management Bus – Address Strobe  
191  
183  
184  
185  
189  
TTL Input  
(5VT)  
Management Bus – Read/Write Control  
CMOS Out- Management Bus – Data Ready  
OD  
CMOS Out- Management Bus – 16 bit Data Bus  
OD  
TTL Input  
(5VT)  
Management Bus – Chip Select  
P_RSTIN#  
TTL In-ST  
(5VT)  
System RESET Input  
190  
192  
187  
P_RSTOUT  
P_INT  
CMOS Output CPU RESET Output  
CMOS Output Management Bus – Interrupt Request  
P_CLK  
TTL Input  
(5VT)  
CPU Clock  
Control Buffer Memory Interface  
60,59,58,57,56,54,53,51, L_D[31:0]  
50,49,48,47,46,45,43,42,  
40,39,38,37,36,34,33,30,  
TTL I/O-TS Local Memory Bus – Data Bit [31:0]  
CMOS Output Local Memory Bus – Address Bit [17:2]  
29,27,26,25,24,23,22,21,  
8,6,5,3,2,1,256,255,254, L_A[18:2]  
253,251,250,248,247,  
246,245,244  
9
L_A[19] /  
L_OE[3]#  
CMOS Output Local Memory Bus – Address Bit [19:18]  
or Memory Read Chip Select [3]  
63, 11, 19  
242, 62, 10, 18  
12,13,14,15  
16  
L_OE[2:0]#  
CMOS Output Local Memory Bus- Read Chip Select  
[2:0]  
L_WE[3:0]#, CMOS Output Local Memory Bus – Write Chip Select  
[3:0]  
L_BWE[3:0]# CMOS Output Local Memory Bus – Byte Write Enable  
[3:0]  
L_ADSC#  
CMOS Output Local Memory Bus – Controller Address  
Status  
66  
L_CLK  
CMOS Output Local Memory Bus – Synchronous Clock  
© 1998 Vertex Networks, Inc.  
5
Rev. 4.5 – February  
1999  
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