MVTX2801
11.5.3 Local Switch Database SBRAM Memory Interface
11.5.3.1 Local SBRAM Memory Interface
Data Sheet
B_CLK
L1
L2
B_D[31:0]
Figure 9 - Local Memory Interface - Input setup and hold timing
B_CLK
B_D[31:0]
B_A[18:2]
L3-max
L3-min
L4-max
L4-min
L6-max
L6-min
B_ADSC#
B_WE#
L10-max
L10-min
L11-max
L11-min
B_OE#
Figure 10 - Local Memory Interface - Output valid delay timing
(SCLK= 133MHz)
Symbol
Parameter
Min (ns)
2.5
Max (ns)
Note:
L1
L2
L3
L4
L6
B_D[31:0] input set-up time
B_D[31:0] input hold time
B_D[31:0] output valid delay
B_A[18:2] output valid delay
B_ADSC# output valid delay
B_WE# output valid delay
B_OE# output valid delay
1
3
3
3
3
3
5
C = 25pf
L
5
5
5
4
C = 30pf
L
C = 30pf
L
L10
L11
C = 25pf
L
C = 25pf
L
Table 13 - AC Characteristics - Local Switch Database SBRAM Memory Interface
97
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
