MVTX2801
11.5.2 Local Frame Buffer ZBT SRAM Memory Interface
11.5.2.1 Local ZBT SRAM Memory Interface A
Data Sheet
LA_CLK
L1
L2
LA_D[63:0]
Figure 7 - Local Memory Interface - Input setup and hold timing
LA_CLK
LA_D[63:0]
LA_A[20:3]
LA_CS[1,0]#
LA_RW#
L3-max
L3-min
L4-max
L4-min
L6-max
L6-min
L9-max
L9-min
Figure 8 - Local Memory Interface - Output valid delay timing
(SCLK= 133MHz)
Parameter
Symbol
Min (ns)
Max (ns)
Note:
L1
L2
L3
L4
L6
L9
LA_D[63:0] input set-up time
LA_D[63:0] input hold time
LA_D[63:0] output valid delay
LA_A[20:3] output valid delay
LA_CS[1:0]# output valid delay
LA_WE# output valid delay
2.5
1
3
5
5
5
5
C = 25pf
L
3
C = 30pf
L
3
C = 30pf
L
3
C = 25pf
L
Table 12 - AC Characteristics - Local frame buffer ZBT-SRAM Memory Interface A
96
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
