MVTX2801
Data Sheet
2.2.2 Read Command
PS_STROBE-
R
A10 A11
A0 A1
START
A9
A2 ...
PS_DI
ADDRESS
COMMAND
D0 D1
DATA
D7
D2 D3 D4 D5 D6
PS_DO
All registers in the MVTX2801 can be modified through this synchronous serial interface.
3.0 Data Forwarding Protocol
3.1 Unicast Data Frame Forwarding
When a frame arrives, it is assigned a handle in memory by the Frame Control Buffer Manager (FCB Manager). An
FCB handle will always be available, because of advance buffer reservations.
The memory (ZBT-SRAM) interface is a 64-bit bus, connected to a ZBT-SRAM domain. The Receive DMA (RxDMA)
is responsible for multiplexing the data and the address. On a port's “turn,” the RxDMA will move 8 bytes (or up to
the end-of-frame) from the port's associated RxFIFO into memory (Frame Data Buffer, or FDB).
Once an entire frame has been moved to the FDB, and a good end-of-frame (EOF) has been received, the Rx
interface makes a switch request. The RxDMA arbitrates among multiple switch requests.
The switch request consists of the first 64 bytes of a frame, containing among other things, the source and
destination MAC addresses of the frame. The search engine places a switch response in the switch response queue
of the frame engine when done. Among other information, the search engine will have resolved the destination port
of the frame and will have determined that the frame is unicast.
After processing the switch response, the Transmission Queue Manager (TxQ manager) of the frame engine is
responsible for notifying the destination port that it has a frame to forward to it. But first, the TxQ manager has to
decide whether or not to drop the frame, based on global FDB reservations and usage, as well as TxQ occupancy
at the destination. If the frame is not dropped, then the TxQ manager links the frame's FCB to the correct
per-port-per-class TxQ. Unicast TxQ's are linked lists of transmission jobs, represented by their associated frames'
FCB's. There is one linked list for each transmission class for each port. There are 8 classes for each of the 4 Gigabit
ports - a total of 32 unicast queues.
The TxQ manager is responsible for scheduling transmission among the queues representing different classes for
a port. When the port control module determines that there is room in the MAC Transmission FIFO (TxFIFO) for
another frame, it requests the handle of a new frame from the TxQ manager. The TxQ manager chooses among the
head-of-line (HOL) frames from the per-class queues for that port, using a Zarlink Semiconductor scheduling
algorithm.
13
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
