MT88E39
Mode 0
Data Sheet
This mode is selected when the MODE pin is low. It is the MT88E41 compatible mode where the FSK data stream
is output as demodulated. Since the MODE pin was IC1 in MT88E41 and connected to Vss, the MT88E39 will work
in mode 0 when placed in a MT88E41 socket.
In this mode, the MT88E39 receives the FSK signal, demodulates it, and outputs the data directly to the DATA pin
(see Figure 11). For each received stop and start bit sequence, the MT88E39 outputs a fixed frequency clock string
of 8 pulses at the DCLK pin. Each DCLK rising edge occurs in the nominal centre of a data bit. DCLK is not
generated for the stop and start bits. Consequently, DCLK will clock only valid data into a peripheral device such as
a serial to parallel shift register or a microcontroller. The MT88E39 also outputs an end of word pulse (Data Ready)
on the DR pin, which indicates the reception of every 10-bit word (counting the start and stop bits) sent from the end
office. DR can be used to interrupt a microcontroller or cause a serial to parallel converter to parallel load its data
into a microcontroller. The mode 0 DATA pin can also be connected to a personal computer’s serial communication
port after converting from CMOS to RS-232 voltage levels.
Mode 1
This mode is selected when the MODE pin is high. In this mode, the microcontroller supplies read pulses at the
DCLK pin (which is now an input) to shift the 8-bit data words out of the MT88E39, onto the DATA pin. The
MT88E39 asserts DR to denote the word boundary and indicate to the microprocessor that a new word has
become available (see Figure 12).
Internal to the MT88E39, the demodulated data bits are sampled and stored. The start and stop bits are stripped
off. After the 8th bit, the data byte is parallel loaded into an 8 bit shift register and DR goes low. The shift register’s
contents are shifted out to the DATA pin on the supplied DCLK’s rising edge in the order they were received.
If DCLK begins while DR is low, DR will return to high upon the first DCLK. This feature allows the associated
interrupt to be cleared by the first read pulse. Otherwise DR is low for half a nominal bit time (1/2400 sec). After the
last bit has been read, additional DCLKs are ignored.
Note that in both modes, the 3-pin interface may also output data generated by speech or other voiceband signals.
The user may choose to ignore these outputs when FSK data is not expected, or force the MT88E39 into its power
down mode.
Power Down Mode
For applications requiring reduced power consumption, the MT88E39 can be forced into power down when it is not
needed. This is done by pulling the PWDN pin high. In power down mode, the oscillator, op-amp and internal
circuitry are all disabled and the MT88E39 will not react to the input signal. DR and CD are at high impedance or at
logic high (modes 0 and 1 respectively). In mode 0, DATA and DCLK are at logic high. The MT88E39 can be
awakened for reception of the FSK signal by pulling the PWDN pin low.
Carrier Detect
The carrier detector provides an indication of the presence of a signal in the FSK frequency band. It detects the
presence of a signal of sufficient amplitude at the output of the FSK bandpass filter. The signal is qualified by a
digital algorithm before the CD output is set low to indicate carrier detection. A 10ms hysteresis is provided to allow
for momentary signal drop out once CD has been activated. CD is released when there is no activity at the FSK
bandpass filter output for 10 ms.
When CD is inactive (high), the raw output of the demodulator is ignored by the data timing recovery circuit (see
Figure 1). In mode 0, the DATA pin is forced high. No DCLK or DR signal is generated. In mode 1, the internal shift
register is not updated and no DR is generated. If DCLK is clocked (in mode 1), DATA is undefined.
Note that signals such as CAS, speech and DTMF tones also lie in the FSK frequency band and the carrier detector
may be activated by these signals. They will be demodulated and presented as data. To avoid false data, the
PWDN pin should be used to disable the FSK demodulator when no FSK signal is expected.
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Zarlink Semiconductor Inc.
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