MT88E39
Data Sheet
IN+
IN-
GS
VRef
CAP
OSC1
OSC2
VSS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
16 PIN SOIC
VDD
IC**
MODE*
PWDN
CD
DR
DATA
DCLK
* Was IC1 in MT88E41
** Was IC2 in MT88E41
Figure 2 - Pin Connections
Pin Description
Pin #
1
2
3
4
5
6
7
8
9
Name
IN+
IN-
GS
V
Ref
CAP
Non-inverting Op-Amp (Input).
Inverting Op-Amp (Input).
Gain Select (Output).
Gives access to op-amp output for connection of feedback resistor.
Voltage Reference (Output).
Nominally V
DD
/2
. This is used to bias the op-amp inputs.
Capacitor.
Connect a 0.1
µF
capacitor to V
SS
.
Description
OSC1
Oscillator (Input).
Crystal connection. This pin can be driven directly from an external clocking
source.
OSC2
Oscillator (Output).
Crystal connection. When OSC1 is driven by an external clock, this pin
should be left open.
V
SS
Power supply ground.
DCLK
3-wire FSK Interface: Data Clock (CMOS Output/Schmitt Input).
In mode 0 (MT88E41
compatible mode - when the MODE pin is logic low) this is a CMOS output which denotes the
nominal mid-point of a FSK data bit.
In mode 1 (when the MODE pin is logic high) this is a Schmitt trigger input used to shift the
FSK data byte out to the DATA pin.
DATA
3-wire FSK Interface: Data (CMOS Output).
In mode 0 (MT88E41 compatible mode - when
the MODE pin is logic low) the FSK serial bit stream is output to DATA as demodulated. Mark
frequency corresponds to logical 1. Space frequency corresponds to logical 0.
In mode 1 (when the MODE pin is logic high) the start and stop bits are stripped off and only
the data byte is stored in a 1 byte buffer. At the end of each word signalled by the DR pin, the
microcontroller should shift the byte out to DATA pin by applying 8 read pulses at the DCLK
pin.
DR
3-wire FSK Interface: Data Ready (Open Drain/CMOS Output).
Active low. In mode 0
(MT88E41 compatible mode - when the MODE pin is logic low) this is an open drain output. In
mode 1 (when the MODE pin is logic high) this is a CMOS output.
This pin denotes the end of a word. Typically, DR is used to interrupt the microcontroller. It is
normally hi-Z or high (modes 0 and 1 respectively) and goes low for half a bit time at the end of
a word. But in mode 1 if DCLK begins during DR low, the first rising edge of the DCLK input
will return DR to high. This feature allows an interrupt requested by DR to be cleared upon
reading the first DATA bit.
10
11
2
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
