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MT8885AE1 参数 Datasheet PDF下载

MT8885AE1图片预览
型号: MT8885AE1
PDF下载: 下载PDF文件 查看货源
内容描述: [DTMF Signaling Circuit, CMOS, PDIP24, LEAD FREE, PLASTIC, MS-011AA, DIP-24]
分类和应用: 电信光电二极管电信集成电路
文件页数/大小: 28 页 / 541 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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MT8885
1.2
Input Configuration
Data Sheet
The input arrangement of the MT8885 provides a differential-input operational amplifier as well as a bias source
(V
Ref
), which is used to bias the inputs at V
DD
/2. Provision is made for connection of a feedback resistor to the op-
amp output (GS) for gain adjustment. In a single-ended configuration, the input pins are connected as shown in
Figure 3.
Figure 4 shows the necessary connections for a differential input configuration.
1.3
Receiver Section
Separation of the low and high group tones is achieved by applying the DTMF signal to the inputs of two sixth-order
switched capacitor bandpass filters, the bandwidths of which correspond to the low and high group frequencies
(see Table 1). The filters also incorporate notches at 350 Hz and 440 Hz for exceptional dial tone rejection. Each
filter output is followed by a single order switched capacitor filter section, which smooths the signals prior to limiting.
Limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of
unwanted low-level signals. The outputs of the comparators provide full rail logic swings at the frequencies of the
incoming DTMF signals.
MT8885
IN+
IN-
C
R
IN
R
F
VOLTAGE GAIN
(A
V
) = R
F
/ R
IN
GS
V
Ref
Figure 3 - Single-Ended Input Configuration
MT8885
C1
R1
IN+
IN-
C2
R4
R5
GS
R3
R2
V
Ref
DIFFERENTIAL INPUT AMPLIFIER
C1 = C2 = 10 nF
R1 = R4 = R5 = 100 kΩ
R2 = 60 kΩ, R3 = 37.5 kΩ
R3 = (R2R5)/(R2 + R5)
VOLTAGE GAIN
INPUT IMPEDANCE
(A
V
diff) - R5/R1
(Z diff) = 2 R1
2
+ (1/ωC)
2
IN
Figure 4 - Differential Input Configuration
4
Zarlink Semiconductor Inc.