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MT8885AE1 参数 Datasheet PDF下载

MT8885AE1图片预览
型号: MT8885AE1
PDF下载: 下载PDF文件 查看货源
内容描述: [DTMF Signaling Circuit, CMOS, PDIP24, LEAD FREE, PLASTIC, MS-011AA, DIP-24]
分类和应用: 电信光电二极管电信集成电路
文件页数/大小: 28 页 / 541 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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MT8885
Integrated DTMF Transceiver with Power
Down and Adaptive Micro Interface
Data Sheet
Features
Central office quality DTMF transmitter/receiver
Single 5 Volt power supply
Adaptive micro interface enables compatibility
with Intel and Motorola processors
DTMF transmitter/receiver power-down via
register control or power-down pin
Adjustable guard time
Automatic tone burst mode
Call progress tone detection to -30 dBm
September 2005
Ordering Information
MT8885AN
24 Pin SSOP
Tubes
MT8885AP
28 Pin PLCC
Tubes
MT8885AE
24 Pin PDIP
Tubes
MT8885AN1
24 Pin SSOP*
Tubes
MT8885AE1
24 Pin PDIP*
Tubes
MT8885ANR
24 Pin SSOP
Tape & Reel
MT8885ANR1
24 Pin SSOP*
Tape & Reel
*Pb Free Matte Tin
-40°C to +85°C
Description
The MT8885 is a monolithic DTMF transceiver with call
progress filter. It is fabricated in CMOS technology
offering low power consumption and high reliability.
The receiver section is based upon the industry
standard MT8870 DTMF receiver. The transmitter
utilizes a switched capacitor D/A converter for low
distortion, high accuracy DTMF signalling. Internal
counters provide a burst mode such that tone bursts
can be transmitted with precise timing. A call progress
filter can be selected allowing a microprocessor to
analyze call progress tones.
The MT8885 utilizes an adaptive micro interface, which
allows the device to be connected to a number of
popular microcontrollers with minimal external logic.
Applications
Credit card systems
Paging systems
Repeater systems/mobile radio
Interconnect dialers
Pay phones
Remote monitor/Control systems
TONE
D/A
Converters
Row and
Column
Counters
Transmit Data
Register
Status
Register
Data
Bus
Buffer
D0
D1
D2
D3
Tone Burst
Gating Cct.
IN+
IN-
GS
OSC1
OSC2
Oscillator
Circuit
Bias
Circuit
V
DD
V
Ref
V
SS
+
-
Dial
Tone
Filter
Control
Logic
Interrupt
Logic
IRQ/CP
High Group
Filter
Low Group
Filter
Control
Logic
Digital
Algorithm
and Code
Converter
Control
Register
A
Control
Register
B
I/O
Control
DS/RD
CS
R/W/WR
RS0
Steering
Logic
Receive Data
Register
PWDN
ESt
St/GT
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1996-2005, Zarlink Semiconductor Inc. All Rights Reserved.