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MT8885AE1 参数 Datasheet PDF下载

MT8885AE1图片预览
型号: MT8885AE1
PDF下载: 下载PDF文件 查看货源
内容描述: [DTMF Signaling Circuit, CMOS, PDIP24, LEAD FREE, PLASTIC, MS-011AA, DIP-24]
分类和应用: 电信光电二极管电信集成电路
文件页数/大小: 28 页 / 541 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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MT8885
V
DD
MT8885
Data Sheet
V
DD
St/GT
ESt
R1
C1
Vc
t
GTA
= (R1C1) In (V
DD
/ V
TSt
)
t
GTP
= (R1C1) In [V
DD
/ (V
DD
-V
TSt
)]
Figure 5 - Basic Steering Circuit
1.5
Guard Time Adjustment
The simple steering circuit shown in Figure 5 is adequate for most applications. Component values are chosen
according to the following inequalities (see Figure 7):
t
REC
t
DPmax
+ t
GTPmax
- t
DAmin
t
REC
t
DPmin
+ t
GTPmin
- t
DAmax
t
ID
t
DAmax
+ t
GTAmax
- t
DPmin
t
DO
t
DAmin
+ t
GTAmin
- t
DPmax
The value of t
DP
is a device parameter (see AC Electrical Characteristics) and t
REC
is the minimum signal duration
to be recognized by the receiver. A value for C1 of 0.1
µF
is recommended for most applications, leaving R1 to be
selected by the designer. Different steering arrangements may be used to select independent tone present (t
GTP
)
and tone absent (t
GTA
) guard times. This may be necessary to meet system specifications which place both accept
and reject limits on tone duration and interdigital pause. Guard time adjustment also allows the designer to tailor
system parameters such as talk-off and noise immunity.
Increasing t
REC
improves talk-off performance since it reduces the probability that tones simulated by speech will
maintain a valid signal condition long enough to be registered. Alternatively, a relatively short t
REC
with a long t
DO
would be appropriate for extremely noisy environments where fast acquisition time and immunity to tone drop-outs
are required. Design information for guard time adjustment is shown in Figure 6. The receiver timing is shown in
Figure 7 with a description of the events in Figure 9.
6
Zarlink Semiconductor Inc.