MT8885
Data Sheet
The MT8885 provides enhanced power-down features. The transmitter and receiver may independently be
powered down via register control.
GS
NC
IN-
IN+
VDD
•
5
6
7
8
9
10
11
24 PIN DIP/SSOP
Figure 2 - Pin Connections
Pin Description
Pin #
Name
24
1
2
3
4
5
6
7
28
1
2
4
6
7
8
9
IN+
IN-
GS
V
Ref
V
SS
OSC1
OSC2
Non-inverting
op-amp input.
Inverting
op-amp input.
Gain Select.
Gives access to output of front end differential amplifier for connection
of feedback resistor.
Reference Voltage
output (V
DD
/2).
Ground (0 V).
Oscillator
input. This pin can also be driven directly by an external clock.
Oscillator
output. A 3.579545 MHz crystal connected between OSC1 and OSC2
completes the internal oscillator circuit. Leave open circuit when OSC1 is driven
externally.
Output from internal DTMF transmitter.
Description
10
11
12
12
13
14
TONE
R/W(WR) (Motorola)
Read/Write
or (Intel)
Write
microprocessor input. CMOS compatible.
CS
Chip Select
input must be gated externally by either address strobe (AS), valid
memory address (VMA) or address latch enable (ALE) signal, depending on
processor used. See Figure 12. Must not be tied low. CMOS compatible.
Register Select
input. Refer to Table 3 for bit interpretation. CMOS compatible.
(Motorola)
Data Strobe
or (Intel)
Read
microprocessor input. Activity on this input is
only required when the device is being accessed. CMOS compatible.
13
14
15
17
RS0
DS
(RD)
2
Zarlink Semiconductor Inc.
TONE
R/W/WR
CS
RS0
NC
DS/RD
IRQ/CP
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
NC
NC
TONE
R/W/WR
CS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VDD
St/GT
ESt
D3
D2
D1
D0
NC
PWDN
IRQ/CP
DS/RD
RS0
4
3
2
1
28
27
26
25
24
23
22
21
20
19
ESt
12
13
14
15
16
17
18
NC
VRef
VSS
OSC1
OSC2
NC
NC
NC
D3
D2
D1
D0
NC
PWDN
28 PIN PLCC
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
