MT8880C
Data Sheet
short delay to allow the output latch to settle, the delayed steering output flag goes high, signalling that a received
tone pair has been registered. The status of the delayed steering flag can be monitored by checking the appropriate
bit in the status register. If Interrupt mode has been selected, the IRQ/CP pin will pull low when the delayed
steering flag is active.
The contents of the output latch are updated on an active delayed steering transition. This data is presented to the
four bit bidirectional data bus when the Receive Data Register is read. The steering circuit works in reverse to
validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the
receiver will tolerate signal interruptions (drop out) too short to be considered a valid pause. This facility, together
with the capability of selecting the steering time constants externally, allows the designer to tailor performance to
meet a wide variety of system requirements.
V
DD
C1
V
DD
St/GT
ESt
R1
Vc
t
GTA
= (R1C1) In (V
DD
/ V
TSt
)
MT8880C
t
GTP
= (R1C1) In [V
DD
/ (V
DD
-V
TSt
)]
Figure 5 - Basic Steering Circuit
Guard Time Adjustment
The simple steering circuit shown in Figure 5 is adequate for most applications. Component values are chosen
according to the formula:
t
REC
= t
DP
+t
GTP
t
ID
=t
DA
+t
GTA
The value of t
DP
is a device parameter (see AC Electrical Characteristics) and t
REC
is the minimum signal duration
to be recognized by the receiver. A value for C1 of 0.1
µF
is recommended for most applications, leaving R1 to be
selected by the designer. Different steering arrangements may be used to select independently the guard times for
tone present (t
GTP
) and tone absent (t
GTA
). This may be necessary to meet system specifications which place both
accept and reject limits on both tone duration and interdigital pause. Guard time adjustment also allows the
designer to tailor system parameters such as talk off and noise immunity.
5
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