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MT8880CSR1 参数 Datasheet PDF下载

MT8880CSR1图片预览
型号: MT8880CSR1
PDF下载: 下载PDF文件 查看货源
内容描述: [DTMF Signaling Circuit, CMOS, PDSO20, 0.300 INCH, LEAD FREE, MS-013AC, SOIC-20]
分类和应用: 电信光电二极管电信集成电路
文件页数/大小: 28 页 / 611 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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MT8880C
Integrated DTMF Transceiver
Data Sheet
Features
Complete DTMF transmitter/receiver
Central office quality
Low power consumption
Microprocessor port
Adjustable guard time
Automatic tone burst mode
Call progress mode
Ordering Information
MT8880CE
MT8880CS
MT8880CN
MT8880CP
MT8880CP1
MT8880CS1
MT8880CE1
MT8880CN1
MT8880CSR
MT8880CPR
MT8880CPR1
MT8880CSR1
20 Pin PDIP
20 Pin SOIC
24 Pin SSOP
28 Pin PLCC
28 Pin PLCC*
20 Pin SOIC*
20 Pin PDIP*
24 Pin SSOP*
20 Pin SOIC
28 Pin PLCC
28 Pin PLCC*
20 Pin SOIC*
*Pb Free Matte Tin
Tubes
Tubes
Tubes
Tubes
Tubes
Tubes
Tubes
Tubes
Tape &
Tape &
Tape &
Tape &
September 2005
ISO
2
- CMOS
Reel
Reel
Reel
Reel
Applications
Credit card systems
Paging systems
Repeater systems/mobile radio
Interconnect dialers
Personal computers
-40°C to +85°C
Description
The MT8880C is a monolithic DTMF transceiver with
call progress filter. It is fabricated in Zarlink
Semiconductor’s ISO
2
-CMOS technology, which
provides low power dissipation and high reliability. The
DTMF receiver is based upon the industry standard
MT8870 monolithic DTMF receiver; the transmitter
utilizes a switched capacitor D/A converter for low
distortion, high accuracy DTMF signalling. Internal
counters provide a burst mode such that tone bursts
can be transmitted with precise timing. A call progress
filter can be selected allowing a microprocessor to
analyze
call
progress
tones.
A
standard
microprocessor bus is provided and is directly
compatible with 6800 series microprocessors.
TONE
D/A
Converters
Row and
Column
Counters
Transmit Data
Register
Status
Register
Data
Bus
Buffer
D0
D1
D2
D3
Tone Burst
Gating Cct.
IN+
IN-
GS
OSC1
OSC2
Oscillator
Circuit
Bias
Circuit
+
-
Dial
Tone
Filter
Control
Logic
Interrupt
Logic
IRQ/CP
High Group
Filter
Low Group
Filter
Control
Logic
Digital
Algorithm
and Code
Converter
Control
Register
A
Control
Register
B
I/O
Control
Φ2
CS
R/W
RS0
Steering
Logic
Receive Data
Register
V
DD
V
Ref
V
SS
ESt
St/GT
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2001-2005, Zarlink Semiconductor Inc. All Rights Reserved.