MT8880C
Data Sheet
MT8880C
OSC1
OSC2
MT8880C
OSC1
OSC2
MT8880C
OSC1 OSC2
3.579545 MHz
Figure 12 - Common Crystal Connection
Microprocessor Interface
The MT8880C employs a microprocessor interface which allows precise control of transmitter and receiver
functions. There are five internal registers associated with the microprocessor interface which can be subdivided
into three categories, i.e., data transfer, transceiver control and transceiver status. There are two registers
associated with data transfer operations.
The Receive Data Register contains the output code of the last valid DTMF tone pair to be decoded and is a read
only register. The data entered in the Transmit Data Register will determine which tone pair is to be generated (see
Figure 7 for coding details). Data can only be written to the transmit register. Transceiver control is accomplished
with two Control Registers (CRA and CRB) which occupy the same address space. A write operation to CRB can
be executed by setting the appropriate bit in CRA. The following write operation to the same address will then be
directed to CRB and subsequent write cycles will then be directed back to CRA. A software reset must be included
at the beginning of all programs to initialize the control and status registers after power up or power reset (see
Figure 16). Refer to Tables 3, 4, 5 and 6 for details concerning the Control Registers. The IRQ/CP pin can be
programmed such that it will provide an interrupt request signal upon validation of DTMF signals or when the
transmitter is ready for more data (Burst mode only). The IRQ/CP pin is configured as an open drain output device
and as such requires a pull-up resistor (see Figure 13).
RS0
0
0
1
1
R/W
0
1
0
1
FUNCTION
Write to Transmit
Data Register
Read from Receive
Data Register
Write to Control
Register
Read from Status
Register
Table 2 - Internal Register Functions
12
Zarlink Semiconductor Inc.
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