MT8880C
Data Sheet
V22L + V23L + .... V2nL + V2
+
2H
V23H + .. V2nH + V2
IMD
THD (%) = 100
V2L + V2
H
Equation 2. THD (%) For a Dual Tone
OUTPUT FREQUENCY
(Hz)
ACTIVE
INPUT
%ERROR
SPECIFIED
697
ACTUAL
699.1
L1
L2
L3
L4
H1
H2
H3
H4
+0.30
-0.49
-0.54
+0.74
+0.57
-0.32
-0.35
+0.73
770
766.2
852
847.4
941
948.0
1209
1336
1477
1633
1215.9
1331.7
1471.9
1645.0
Table 1 - Actual Frequencies Versus Standard Requirements
DTMF Clock Circuit
The internal clock circuit is completed with the addition of a standard television colour burst crystal. The crystal
specification is as follows:
Frequency:
3.579545 MHz
±0.1%
Frequency Tolerance:
Resonance Mode:
Load Capacitance:
Parallel
18 pF
Maximum Series Resistance: 150 ohms
Maximum Drive Level:
2 mW
e.g. CTS Knights MP036S
Toyocom TQC-203-A-9S
A number of MT8880C devices can be connected as shown in Figure 12 such that only one crystal is required.
Alternatively, the OSC1 inputs on all devices can be driven from a TTL buffer with the OSC2 outputs left
unconnected.
11
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
