MT8880C
Data Sheet
VDD
MT8880C
C3
R4
VDD
IN+
C1
R1
C2
St/GT
ESt
DTMF/CP
INPUT
IN-
GS
R3
R2
D3
VRef
VSS
OSC1
OSC2
TONE
R/W
CS
D2
D1
R5
D0
X-tal
RL
To µP
or µC
IRQ/CP
Φ2
DTMF
OUTPUT
C4
RS0
Notes:
R1, R2 = 100 kΩ 1%
R3 = 374 kΩ 1%
R4 = 3.3 kΩ 10%
R5 = 4.7 MΩ 10%
RL = 10 k Ω (min.)
* Microprocessor based systems can inject undesirable noise into
the supply rails. The performance of the MT8880 can be optimized
by keeping noise on the supply rails to a minimum. The decoupling
capacitor (C3) should be connected close to the device and ground
loops should be avoided.
C1 = 100 nF 5%
C2 = 100 nF 5%
C3 = 100 nF 10%*
C4 = 10 nF 10%
X-tal = 3.579545 MHz
Figure 13 - Application Circuit (Single-Ended Input)
15
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
