MT8809
Change Summary
Changes from the September 2005 issue to the September 2011 issue.
Data Sheet
Page
1
Item
Ordering Information
Change
Removed leaded packages as per PCN notice.
AY2
STROBE
CS
DATA
VSS
X0
X2
X4
X6
RESET
Y7
Y6
Y5
Y4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AY1
AY0
AX2
AX1
AX0
X1
X3
X5
X7
VDD
Y0
Y1
Y2
Y3
4
3
2
1
28
27
26
DATA
CS
STROBE
AY2
AY1
AY0
AX2
28 PIN PLASTIC DIP
Figure 2 - Pin Connections
Pin Description
Pin #
1
2
Name
AY2
AY2 Address Line (Input).
Description
STROBE
STROBE (Input):
enables function selected by address and data. Address must be stable
before STROBE goes low and DATA must be stable on the rising edge of STROBE. Active
Low.
CS
DATA
V
SS
X0, X2,
X4, X6
RESET
Chip Select (Input):
this is used to select the device. Active Low.
DATA (Input):
a logic high input will turn on the selected switch and a logic low will turn off
the selected switch. Active High.
Ground Reference.
X0, X2, X4 and X6 Analog (Inputs/Outputs):
these are connected to the X0, X2, X4 and
X6 rows of the switch array.
Master RESET (Input):
this is used to turn off all switches regardless of the condition of
CS. A 100 k internal pull-up resistor is also provided. This can be used in conjunction
with a 0.1
F
capacitor (connected to the RESET pin) to perform power-on reset of the
device. Active Low.
Y7 - Y0 Analog (Inputs/Outputs):
these are connected to the Y0 - Y7 columns of the
switch array.
3
4
5
6-9
10
11-18
Y7 - Y0
2
Zarlink Semiconductor Inc.
Y6
Y5
Y4
Y3
Y2
Y1
Y0
12
13
14
15
16
17
18
VSS
X0
X2
X4
X6
RESET
Y7
5
6
7
8
9
10
11
25
24
23
22
21
20
19
AX1
AX0
X1
X3
X5
X7
VDD
28 PIN PLCC
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
