DiSEqC Control MT312
Def
NAME
DISEQC2 FIFO 120
Refer to preceding section for buffer overflow.
ADR
B7
B6
B5
B4
B3
B2
B1
B0
hex
Reserved
Par
error
Par
bit
R
00
The received bytes are read from this location with 2-wire bus auto-increment bit set to zero. The received
bytes will be available in the order received, i.e. the buffer is a First In First Out (FIFO) memory.
Note that two read operations are needed for each byte. The first read operation will give the data byte and the
second will provide the associated parity bit(B0) and the parity-error bit(B1), the other 6 bits will be zero. For
example, if four bytes are received, then eight read operations (with auto-increment bit set to zero) are needed
to get all data bytes as well as the parity bits.
The number of bytes received is given by bits B3-0 of DISEQC2 STATUS BYTES register 119.
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