QPSK Demodulator MT312
The Viterbi decoder will search for a signal with the code rates selected by this register. If one code rate is
selected, the MT312 will search for a signal with only that code rate. If the code rate is unknown then all B5:0
may be set, when the MT312 will search all code rates. It is possible to choose the starting point for the code
rate search by setting a bit in VIT SETUP[B3:1] register (86). After searching for a signal with the initial code
rate, if no signal is found the search proceeds to the next higher code rate, see 69.
In the DSS mode the code rate is not specified using VIT MODE register. If any of the two DSS bits of
Configuration Register (127) is set, then the code rates selected by the VIT MODE register are ignored. The
DSS code rate selection is carried out as described in section 1.1, see 10.
The result of the search is reported in the FEC STAT register (6), see 49.
6.1.3 QPSK Control. Register 26 (R/W)
Def
hex
NAME ADR
B7
B6
B5
B4
B3
B2
B1
B0
QPSK
CTRL
26 Reserved
Q
IQ SP
Reserved Reserved Reserved AFC Reserved ROLL R/W
20
00
M
B7:
Reserved
Must be set low.
B6:
Q IQ SP
Swap I and Q inputs before QPSK demodulation to overcome spectral inversion
caused by the receiver front-end, for example through the swapping I and Q wires on
the board.
High = I-Q swap
Low = No I-Q swap
B5:
B4:
B3:
B2:
B1:
B0:
Reserved
Reserved
Reserved
AFC M
Must be set low.Q MANHigh = QPSK manual programming
Must be set low.OP CALHigh = Output calculation disable
Must be set low.FLD LKHigh = Use Frequency Lock Detector lock
High = Use AFC mode, for low Symbol rates only, < 10MSym/s.
Must be set low.
Reserved
ROLL 20
High = Roll-off 0.20
Low = Roll-off 0.35
If any of the two DSS control bits of the Configuration Register (127) is active (see section 1.1 10), then bit B0
(ROLL 20) is ignored and the matched filter root-raised-cosine roll-off factor is taken as 0.20. Hence bit only
allows the choice of roll-off in the DVB mode.
39
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