MA808
RCK I/P
RXI I/P
X 0 0 1 1 0 1 1
X 1 X X X X X X
TS0S
TS1
TS2
TS30
TS31
TS0N
TSZ I/P
BIT NO. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
LCK I/P
TS0
FRS I/P
16th BIT
TS1
1st BIT OF TIME SLOT 2
RXO1 O/P
X 0 0 1 1 0 1 1
RXO2 O/P
X 0 1 1 1 0 1 1
Figure 5: Timing diagram - basic mode: general operation of frame alignment
DATA I/P
TSOS TSON
TSOS TSON
TSOS TSON
TSOS
TSON TSOS
TSON
TSOS
TSON
SA1 I/P
ALM I/P
RXO1 O/P
X00110011
X00110011
X00110011 X00110011
X00110011
X1XXXXXX
X1XXXXXX
X1XXXXXX
X1XXXXXX
X1XXXXXX
RXO2 O/P
X00110011
X00110011
X1XXXXXX
X00110011
X00110011
X1XXXXXX
X1XXXXXX
X1XXXXXX
Figure 6: Timing diagram: protocol timings of the alarm signals
5
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
