MA808
OPERATION IN BASIC MODE (M =V
SS
)
FRAME ALIGNMENT
The remote non-return-to-zero (NRZ) binary PCM data
stream (RXI) required to be aligned must be applied to the
frame aligner along with a synchronous clock (RCK). A time
slot zero impulse (TSZ) as shown in Fig. 5 is also required to
define the start ot the frame of input data.
A local clock (LCK) provides the timing from which the
output data is clocked. Frame reset pulse (FRS) is the data
output timing pulse. The MA808 aligns the 16th bit of the
incoming data to this pulse, as shown in Fig. 5, and the two
NRZ binary outputs RXO1 and RXO2 are produced. RXO1 is
purely a retimed version of the input data. RXO2 has the third
bit of all time slot zero locations of the input data inverted,
thereby deliberately corrupting the frame sync. and the frame
sync. verification words. Once synchronisation has been
established
FRS
may be removed. If synchronisation is lost,
FRS
must be reapplied in order to permit resynchronisation to
be established.
SLIP COMPENSATION
Small differences in frequency between the local and
remote clocks (LCK and RCK) are compensated for by
the repetition of the previous frame, (‘slipping in’) or the
omission of one complete frame of data (‘slipping out’).
INPUT ALARMS
Two input alarms (SA1 and ALM) are provided which will
set data output(s) to an ‘all ones’ condition. ALM sets only
RXO2 and
SA1
sets both RXO1 and RXO2 high (Fig. 6).
TEST FEATURES
The operation of the internal memory of the MA808 is
continuously monitored by performing a check sum
comparison of the input and output data signals RXI and
RXO1. When an error is detected, the time slot zero words of
RXO1 and RXO2 are set ‘high’.
When a ‘low’ is applied to test input T3, the outputs RXO1,
RXO2 and CK are forced into a high impedance condition,
thereby allowing associated circuitry to be tested
independently of the MA808. Note that this facility is only
available in the basic mode of operation.
OPERATION IN ENHANCED MODE (M=V
DD
)
When configured in the enhanced mode the chip performs
time slot zero (TS0) recovery in addition to the frame alignment
function. TS0 recovery may also be performed independently.
FRAME ALIGNMENT
The operation of frame alignment is essentially the same
as the basic mode, except that the TSZ pulse is an output
rather than an input, in accordance with the operation of the
TS0 receiver, as shown in Fig. 7. The operation of the input
alarms to set the output data ‘high’ is the same as described in
the basic mode (Fig. 6).
TIME SLOT ZERO RECEIVER
Two output signals (TSZ and
CCR)
are provided so that the
time slot zero receiver may be used independently of the frame
alignment function.
CCR
is a channel reset pulse (as shown in
Fig. 7) which goes ‘low’ for one RCK period following a sync.
word (every alternate frame) when the device is in sync. When
the device is out of sync. the reset pulse occurs after each time
slot zero.
The TS0 receiver accesses information contained within
time slot zeros and processes it to offer the facilities of
synchronisation alarm (SA), error output (ER) and time slot
zero spare bits (Q1S, Q1N, Q3N-Q8N).
SYNCHRONISATION ALARM (SA)
SA indicates loss of sync. as shown in Fig. 8. With the
frame aligner operating in sync., SA will be ‘low’. Following the
receipt of 3 successive sync. words containing errors, SA will
become active. SA will remain ‘high’ until the correct
synchronising sequence as defined in CCITT
recommendations G732 has been received.
ERROR OUTPUT (ER)
A logic signal, ER, indicating errors in sync. words, is
provided as shown in Fig. 8, from which an AIS alarm may be
generated. ER is activated at the beginning of the second bit of
time slot 1 two frames after the receipt of a sync. word
containing errors. If successive sync. words contain errors, the
signal will remain active.
If synchronisation is lost, ER will remain active but will go
‘low’ for one period of the remote clock during the second bit of
time slot 1, two frames after the receipt of the last valid sync.
word, as long as synchronisation is not regained at this time.
If synchronisation is regained, ER will go ‘low’ for the two
frames following the sync. word which caused synchronisation
to be regained. The signal indicating an error in the sync. word
two frames prior to synchronisation being regained will be
delayed by one further sync. frame period. Consequently, it
may be concluded that all errors in sync. words are accounted
for in this signal, hence error monitoring in accordance with
CCITT recommendation G732.3.1.6.1 may be performed.
TIME SLOT ZERO SPARE BITS
The spare bits contained in both time slot zero words are
converted from serial to parallel format (Q1N, Q3N-Q8N inc.
and Q1 S) are shown in Fig. 9.
2
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
