MA808
PIN DESCRIPTIONS - BASIC MODE
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Def.
T1
RXI
ALM
R
T2
TSZ
RCK
CK
FRS
LCK
T3
V
SS
RXO1
RXO2
SA1
M
NC
NC
NC
T4
T5
T6
T7
V
DD
Function
Test input
Data input
Alarm input
Reset input
Test input
TSO input
Clock input
256kHz output
Timing input
Clock input
Test input
Negative supply
Data output
Data output
Set to all 1s input
Mode input
No connection
No connection
No connection
Test input
Test input
Test output
Test output
Positive supply
Description
Active high. To be tied to logic low during normal operation.
Recovered distant data input.
A logic high on this input sets RXO2 to an all 1 s condition.
‘Low’ resets the device tied ‘high’ normally.
Active low. To be tied to logic high during normal operation.
Remote TS0 timing signal.
Recovered distant clock in sync. with RXI.
256kHz square wave clock output synchronous with LCK.
Data output timing pulse coincident with 16th bit of the local clock.
Local clock input.
Active low. To be tied to logic high during normal operation.
Nominally 0V.
Retimed data output to LCK.
As RXO1 except that bit 3 of each TS0 word is inverted.
A logic low sets RXO1 and RXO2 to an all 1s condition.
Connected to Vss for basic mode operation.
To be left O/C during normal operation.
To be left O/C during normal operation.
To be left O/C during normal operation.
Active when clocked by LCK (pin 10). To be tied to logic low during normal operation.
Active when clocked by RCK (pin 7). To be tied to logic low during normal operation.
To be left O/C during normal operation.
To be left O/C during normal operation.
Nominally + 5V.
PIN DESCRIPTIONS - ENHANCED MODE
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Def.
CCR
RXI
ALM
ER
SA
TSZ
RCK
CK
FRS
LCK
Q8N
V
SS
RXO1
RXO2
SA1
M
Q7N
Q6N
Q5N
Q4N
Q3N
Q1 N
Q1 S
V
DD
Function
Channel reset
Data input
Alarm input
Error output
Sync. alarm O/P
TSO output
Clock input
256kHz output
Timing input
Clock input
Output signal
Negative supply
Data output
Data output
Set to all 1s input
Mode input
Output signal
Output signal
Output signal
Output signal
Output signal
Output signal
Output signal
Positive supply
Descrlption
An output used to reset other devices within the system.
Recovered distant data input.
A logic high on this input sets RXO2 to an all 1 s condition.
A TS0 word error is signalled when ER goes to logic high.
Loss of sync. is signalled when SA goes to logic high.
Remote TS0 output signal, (internally connected to the on-chip frame aligner).
Recovered distant clock in sync. with RXI.
256kHz square wave clock output synchronous with LCK.
Data output timing pulse coincident with 16th bit of the local clock.
Local clock input.
Signal corresponding to bit 8 of the TS0 sync. verification word.
Nominally 0V
Retimed data output to LCK
As RXO1 except that bit 3 of each TS0 word is inverted.
A logic low sets RXO1 and RXO2 to an all 1s condition.
Connected to V
DD
for enhanced mode operation.
Signal corresponding to bit 7 of the TS0 sync. verification word.
Signal corresponding to bit 6 of the TS0 sync. verification word.
Signal corresponding to bit 5 of the TS0 sync. verification word.
Signal corresponding to bit 4 of the TS0 sync. verification word.
Signal corresponding to bit 3 of the TS0 sync. verification word.
Signal corresponding to bit 1 of the TS0 sync. verification word
Signal corresponding to bit 1 of the TS0 sync. word.
Nominally +5V.
3
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
