MA808
R
LCK RCK TSZ FRS SA1 ALM
CONTROL
LOGIC
R
RCK
T3
WRITE
BIT
COUNTER
READ
BIT
COUNTER
R
LCK
T3
R
RCK
UNALIGNED
DATA
INPUT
RXI
R
SIPO
RAM
R
PISO
LCK
ALIGNED
DATA
INPUT
RXO1
RXO2
LCK
T6
R
RCK
T2
T4
R
T3
PARITY
SIPO
PARITY
WRITE
ADDRESS
COUNTER
ADDRESS
MULTI-
PLEXER
READ
ADDRESS
COUNTER
R
T3
RANGE
DETECTOR
CK
CONTROL
LOGIC
R
LCK RCK TSZ FRS SA1 ALM
Figure 3: Frame aligner block diagram
CCR ER SA TSZ
RXI
R
RCK
T1
T2
Q1S
Q1N
Q3N
Q4N
Q5N
Q6N
Q7N
Q8N
RCK
DECODER
TIME
SLOT
ZERO
TO
PARALLEL
CONVERTER
R
RCK
T2
SYNC
COUNTER
SYNC WORD
DETECTOR AND
STATE CONTROL
R
RCK
T7
4
Figure 4: TSO receiver block diagram