Le58083
Data Sheet
SOP Control Byte Command Format
SOP 1. Deactivate Channel (Standby Mode)
GCI Command
(00h)
D7
D6
D5
0
D4
0
D3
0
D2
0
D1
0
D0
Command
0
0
0
In the Deactivated (Standby) mode:
All of the programmed information is retained.
The upstream and downstream Monitor and SC channels remain active.
The B channel for an inactive channel is idle, no data is received or transmitted.
The analog output (VOUT) is disabled and biased at VREF.
The Channel Status (CSTAT bit in the SLIC device I/O and Status Bits register is set to 0.
SOP 2. Software Reset
GCI Command
(02h)
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
1
D0
0
Command
The action of this command is identical to that of the RST pin except it only operates on the addressed channel and does not
reset the ground key filtering interval.
SOP 3. Hardware Reset
GCI Command
(04h)
D7
0
D6
0
D5
0
D4
0
D3
0
D2
1
D1
0
D0
0
Command
The Hardware reset command is equivalent to pulling the RST pin on a four-channel group of the device low. This command
resets all four channels of the device. The action of the Hardware reset function is described in Reset States on page 37.
SOP 4. Activate Channel (Operational Mode)
GCI Command
(0Eh)
D7
0
D6
0
D5
0
D4
0
D3
1
D2
1
D1
1
D0
0
Command
This command places the addressed channel of the device in the Active mode. No valid B-Channel data is transmitted until after
the second FSC pulse is received following the execution of the Activate command. The Channel Status (CSTAT) bit in the SLIC
device I/O and Status Bits register is set to 1.
SOP 5. Write/Read Configuration Register 1 (CR1), Operating Conditions
GCI Command
(70/71h)
Operating Conditions (Configuration Register 1, CR1)
D7
D6
D5
D4
D3
D2
D1
D0
Command
I/O Data
0
1
1
1
0
0
0
R/W
TON
CTP
CRP
HPF
LRG
ATI
ILB
FDL
Configuration register CR1 enables or disables test features and controls feeding states. The reset value of CR1 = 04H
73
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
