Le58083
Data Sheet
SOP 8. Write/Read Configuration Register 4 (CR4), SLIC Device I/O Direction and Status Bits
GCI Command
(54/55h)
SLIC Device I/O Direction and Status Bits (Configuration Register 4, CR4)
D7
D6
D5
D4
D3
D2
D1
D0
Command
I/O Data
0
1
0
1
0
1
0
R/W
RSVD
CSTAT
CFAIL
IOD5
IOD4
IOD3
IOD2
IOD1
Pins CD1, CD2 and C3 through C5 are set to Input or Output modes individually.
RSVD: Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
Channel Status (Read only, write as 0)
CSTAT = 0
Channel is inactive (Standby mode)
Channel is active
CSTAT = 1
Clock Fail (Read only, write as 0; Global status bit)
CFAIL = 0
CFAIL = 1
The internal clock is synchronized to frame sync
The internal clock is not synchronized to frame sync
The CFAIL bit is universal for the Le58083 Octal SLAC device and is independent of the channel addressed.
IOD1–IOD5
Programmable I/O direction control (CD1, CD2, C3, C4, C5 pins)
*0 = Pin is set as an input port
1 = Pin is set as an output port
*Power Up and Hardware Reset (RST) Value = 00h
SOP 9. Write/Read Configuration Register 5 (CR5), Operating Mode
GCI Command
(4A/4Bh)
Operating Mode (Configuration Register 5, CR5)
D7
0
D6
1
D5
D4
D3
1
D2
0
D1
1
D0
Command
I/O Data
0
0
R/W
RSVD
VMODE
LPM
RSVD
RSVD:
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
VOUT Mode (Global parameter)
VMODE = 0*
VOUT = VREF through a resistor when channel is inactive
VOUT high impedance when channel is inactive.
VMODE = 1
Low Power Mode (Global parameter)
LPM
LPM reduced the power in the QSLAC device, but it is not needed and not used in the
Le58083 Octal SLAC device
Power Up and Hardware Reset (RST) Value = 0Fh
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