™
Le58083
Low Voltage Subscriber Line Audio-processing Circuit
VE580 Series
APPLICATIONS
■
Codec function on telephone switch line cards
RELATED LITERATURE
■
080753 Le58QL02/021/031 QLSLAC
™
Data Sheet
■
080754 Le58QL061/063 QLSLAC
™
Data Sheet
■
080761 QSLAC™ to QLSLAC™ Design Conversion
Guide
FEATURES
■
Low-power, 3.3 V CMOS technology with 5 V tolerant
digital inputs
■
Pin programmable PCM/MPI or GCI interface
■
Software and coefficient compatible to the VE580
series QLSLAC™ devices
(PCM/MPI mode)
—
—
—
—
—
■
080758 QSLAC™ to QLSLAC™ Guide to New Designs
DESCRIPTION
The Le58083 Octal Low Voltage Subscriber Line Audio-
Processing Circuit (Octal SLAC™) devices integrate the key
functions of analog line cards into high-performance, very-
programmable, eight-channel codec-filter devices. The
Le58083 Octal SLAC devices are based on the proven design
of
Zarlink’s
reliable SLAC device families. The advanced
architecture of the Le58083 Octal SLAC devices implements
eight independent channels and employs digital filters to allow
software control of transmission, thus providing a cost-effective
solution for the audio-processing function of programmable line
cards. The Le58083 Octal SLAC devices are software and
coefficient compatible to the VE580 series QLSLAC™ devices.
Advanced submicron CMOS technology makes the Le58083
Octal SLAC devices economical, with both the functionality and
the low power consumption needed in line card designs to
maximize line card density at minimum cost. When used with
multiple
Zarlink
SLIC devices, an Le58083 Octal SLAC device
provides a complete software-configurable solution to the
BORSCHT functions.
■
Standard PCM/microprocessor interface
Single or Dual PCM ports available
Time slot assigner (up to 128 channels per port)
Clock slot and transmit clock edge options
Optional supervision on the PCM highway
1.536, 1.544, 2.048, 3.072, 3.088, 4.096, 6.144, 6.176,
or 8.192 MHz master clock derived from MCLK or PCLK
— µP access to PCM data
— Real Time Data with interrupt (open drain or TTL)
— Broadcast mode
■
General Circuit Interface (GCI mode)
— Control and PCM data on a single port
— 2.048 Mbits/s data rate
— 2.048 MHz or 4.096 MHz clock option
■
Performs the functions of eight codec/filters
■
Software programmable:
— SLIC device input impedance and Transhybrid balance
— Transmit and receive gains and Equalization
— Programmable Digital I/O pins with debouncing
BLOCK DIAGRAM
ANALOG
GCI/PCM
Interface
■
A-law, µ-law, or linear coding
■
Built-in test modes with loopback, tone generation,
and µP access to PCM data
DXA/DU
DRA/DD
VIN
(1-8)
Signal
Processing
Channels 1-8
TSCA
■
■
■
■
Mixed state (analog and digital) impedance scaling
Performance guaranteed over a 12 dB gain range
Supports multiplexed SLIC device outputs
256 kHz or 293 kHz chopper clock for
Zarlink
SLIC
devices with switching regulator
VOUT
(1-8)
PCM & GCI Interface
&
Time Slot Assigner
(TSA)
DXB
DRB
TSCB
VREF_1, VREF_2
SLIC
CONTROLS
■
Maximum channel bandwidth for V.90 modems
CD1
(1-8)
CD2
(1-8)
C3
(1-8)
C4
(1-8)
C5
(1-8)
C6
(1-8)
C7
(1-8)
Clock
&
Reference
Circuits
FS/FSC
PCLK/DCL
MCLK_1, MCLK_2
ORDERING INFORMATION
Device
Le58083ABGC
Package
121-pin BGA (Green package)*
SLIC
Interface
(SLI)
DCLK-S0_1, DCLK-SO_2
CS/PG_1, CS/PG_2
GCI Control Logic &
Microprocessor Interface
(MPI)
DIO-S1_1, DIO-S1_2
INT_1, INT_2
*Green package meets RoHS Directive 2002/95/EC of the European
Council to minimize the environmental impact of electrical equipment.
RST
Document ID#
080921
Date:
Rev:
E
Version:
Distribution:
Public Document
Sep 18, 2007
2
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
