GP4020
Associated
circuit block
Pin No.
Signal Name
Type
Description
System Data bit 7
System Output Enable, active low
System Write Enable bit 1, active low
System Write Enable bit 0, active low
System Data bit 8
Notes
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
SDATA[7]
NSOE
NSWE[1]
NSWE[0]
SDATA[8]
SDATA[9]
VDD
SDATA[10]
SDATA[11]
GND
SDATA[12]
SDATA[13]
SDATA[14]
SDATA[15]
SADD[18]
I/O
I/O
I/O
I/O
I/O
I/O
PWR
I/O
I/O
PWR
I/O
MPC
MPC
MPC
MPC
MPC
MPC
1
1
1
1
1
1
System Data bit 9
MPC
MPC
System Data bit 10
System Data bit 11
1
1
MPC
MPC
MPC
MPC
MPC
System Data bit 12
System Data bit 13
System Data bit 14
System Data bit 15
System Address bit 18
1
1
1
1
I/O
I/O
I/O
I/O
39
40
41
42
43
44
45
46
47
48
49
SADD[17]
SADD[16]
GND
I/O
I/O
MPC
MPC
System Address bit 17
System Address bit 16
PWR
I/O
SADD[15]
SADD[14]
VDD
MPC
MPC
System Address bit 15
System Address bit 14
I/O
PWR
I/O
SADD[13]
SADD[12]
SADD[11]
SADD[10]
SADD[9]
MPC
MPC
MPC
MPC
MPC
System Address bit 13
System Address bit 12
System Address bit 11
System Address bit 10
System Address bit 9
I/O
I/O
I/O
I/O
50
51
SADD[8]
SWAIT
I/O
I
MPC
MPC
System Address bit 8
System Wait input - allows
wait-states to be inserted into the
current Firefly clock cycle.
52
53
NSUB
IEXTINT2
O
I
MPC
INTC
System Upper Byte, active low.
Interrupt source 2 input
1,2
(for external interrupts).
54
55
MULTI_FNIO
DISCIO
I/O
I/O
I
PCL
PCL
Multi-function Input / Output. Used to set
Boot Up ROM area, and source either
100kHz square wave or System Clock.
Discrete Input / Output.
3
Used either as input or to source
RF_Power_Down control signal or TIC.
PLL Lock Indicator input from RF section.
When high this signal indicates that the
PLL within the RF section is in lock and
the master-clock inputs have stabilised.
VDD Supply for CLK_T & CLK_I input
block in the System Clock Generator. This
pin should be well decoupled to pin 60
(GND) to ensure optimum noise immunity
Master Clock Input from RF front end
40MHz 100mV rms.
56
57
RF_PLL_LOCK
A1VDD
INTC /PCL
PWR
SCG
58
59
CLK_T
CLK_I
I
I
SCG
SCG
4
4
Inverted Master Clock Input from RF
front end: 40MHz 100mV rms.
Cont…
Table 1 - Pin descriptions (continued)
4
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
