YGV629
z
CPU Interface
・Parallel Interface
No.
Items
PS2-0: setup time
PS2-0: hold time
CS_N: setup time
CS_N: hold time
D7-0: output data turn on time
D7-0: output data turn off time
D7-0: output data valid delay time
D7-0: output data hold time
WAIT_N,READY_N: turn on time
Symbol
tsA
thA
tsCS
thCS
tonD
toffD
tdD
Min.
Typ.
Max.
Unit Note
1
2
3
4
5
6
7
8
9
4
0
0
0
0
1
1
2
2
10
0
thD
0
0
ns
tonWAIT
tdWAIT
toffWAIT
tsD
10 WAIT_N,READY_N: valid delay time
11 WAIT_N,READY_N: turn off time
12 D7-0: input data setup time
13 D7-0: input data hold time
14 READY_N: hold time
15 command pulse active time
16 command pulse inhibit time
17 command cycle time
13
10
tSYCLK+10
0
thD
thREADY
taCMD
tiCMD
tcCMD
0
2tSYCLK
4tSYCLK
6tSYCLK
3
3
3
Note1) Regulations for WR_N, RD_N signal. However, in CS_N control, these regulations are for CS_N.
Note2) Conditions to be the control for WR_N, RD_N control. if it does not meet the regulation, the control turns
into the CS_N control.
Note3) The command pulse means a low active pulse, which is made by the OR operation performed between
each of WR_N and RD_N signal and CS_N signal.
・CPU Read Cycle
PS2-0
1
2
CS_N
RD_N
D7-0
3
4
8
6
5
High-z
High-z
High-z
High-z
10
7
7
11
11
9
9
WAIT_N
14
High-z
High-z
READY_N
-18-
4GV629A50
YAMAHA [ YAMAHA CORPORATION ]
